| Topic |
Sub-topic |
| LESSON 1 THEORY (2 h.). INTRODUCTION TO COMPLEX DIGITAL SYSTEM DESIGN AND SYNTHESIS. |
1.1.- Introduction.
1.2.- Types of digital integrated circuits. Microprocessors. DSPs. ASICs. FPGAs.
1.2.1.- Comparative analysis.
1.3.- Field Programmable Gate Arrays (FPGAs).
1.4.- Complex application specific digital system design by means of FPGAs.
1.4.1.- Sequential processing systems. Operational unit. Control Unit.
1.4.2.- Continuous processing systems.
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| LESSON 2 THEORY (2 h.). ADVANCED DIGITAL SYSTEM DESIGN. |
2.1.- Introduction.
2.2.- General rules for the design of digital systems.
2.2.1.- Hierarchical design.
2.2.2.- Technology independent design.
2.2.3.- Design timing.
2.2.4.- Design for reuse.
2.2.5.- Design for verificability.
2.2.6.- Design documentation.
2.3.- Intellectual Property (IP) cores.
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| LESSON 3 THEORY (2 h.). INTRODUCTION TO SYNTHESIS OF DIGITAL SYSTEMS DESCRIBED IN VHDL. |
3.1.- Introduction.
3.2.- Definition of synthesis. Basic concepts on synthesis.
3.3.- Conversion of a VHDL description to real hardware. Differences between the original VHDL model and the result of the synthesis / implementation. Timing simulation model.
3.4.- Recommendations for the description in VHDL synthesisable of distinct types of circuits.
3.5.- Examples of synthesisable models of commonly used circuits.
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| LESSON 4 THEORY (4 h.). VHDL ADVANCED SENTENCES. |
4.1.- Introduction.
4.2.- Access to files.
4.2.1.- Memory initialisation.
4.2.2.- Testbench stimuli.
4.3.- Generic data type. Parameterisable circuits.
4.4.- Libraries and packages.
4.5.- Subprograms.
4.5.1.- Functions.
4.5.2.- Procedures.
4.6.- Conditional compilation.
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| LESSON 5 THEORY (6 h.). VHDL FOR SYNTHESIS. RESTRICTIONS. |
5.1.- Introduction.
5.2.- IEEE standard for synthesis.
5.3.- Time sentences (After, Wait).
5.4.- Loops (Loop). Loops generate.
5.5.- Real data type. Type conversion.
5.6.- Complex arithmetical operations. Division (/).
5.7.- Complex mathematical functions. (Without, Cos, Log).
5.8.- Two-dimensional matrices. (Array).
5.9.- Exercises of non- synthesisable models and equivalent synthesisable circuits.
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| LESSON 6 THEORY (2 h.). ARITHMETICAL CIRCUITS DESIGN IN VHDL. |
6.1.- Introduction.
6.2.- Representation of binary numbers with decimal part. Fixed point. Floating point.
6.3.- Design of fixed point applications.
6.4.- Design of floating point applications.
6.5.- Implementation of arithmetical circuits in FPGAs.
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| LESSON 7 THEORY (1 h.). VERIFICATION OF COMPLEX DIGITAL SYSTEMS. |
7.1.- Introduction.
7.2.- Verification through simulation.
7.2.1.- Signals. Delay models. Definition of ‘driver’.
7.2.2.- Design analysis and simulation. Simulation cycle. Delta delay.
7.2.3.- Recommendations for VHDL simulation. Examples. Testbench design.
7.2.4.- Differences between functional and timing simulation.
7.3.- Verification through timing analysis.
7.4.- Verification through test in a development board.
7.5.- Exercises.
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| LESSON 1 LABORATORY (6 h. TYPE B). PRACTICAL TUTORIAL OF DIGITAL SYSTEM DESIGN AND SYNTHESIS. |
1.1.- Introduction.
1.2.- Basic digital system design in synthesisable VHDL.
1.3.- Testbench design in VHDL.
1.4.- Implementation of digital systems in FPGAs.
1.5.- Testing digital systems.
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| LESSON 2 LABORATORY. (15 h. = 8 H. TYPE B + 7 h. TYPE C). DESIGN OF A MEDIUM-COMPLEXITY DIGITAL SYSTEM IN SYNTHESISABLE VHDL. |
2.1.- Introduction. Task explanation. (2 h. TYPE B)
2.2.- Project based learning. Discussions on the most suitable approach. (6 h. TYPE C)
2.2.- Design of a medium-complexity digital system in synthesisable VHDL. (6 h. TYPE B)
2.3.- Oral presentation. (1 h. TYPE C)
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