Guia docente 2014_15
Escola de Enxeñaría de Telecomunicación
Máster Universitario en Enxeñaría de Telecomunicación
 Subjects
  Codeseño Hardware/Software de Sistemas Empotrados
   Assessment
  Description Qualification
Integrated methodologies Problem Based Learning.
Resolution of exercises and theoretical problems. The majority of them will be focused on the theoretical approach to the design of a peripheral of an embedded system.
The problems will be based on the theoretical topics.
It will be necessary to show to the professor the operation of each one of the circuits and programs.
The correct application of the theoretical concepts to the problems will be assessed, based on the published criteria.
It will be necessary to deliver the documentation requested by the professor for each one of the exercises.
<br>Through this methodology the outcomes CB5, CG1, CG8, CE11/TT11 and CE12/TT12 are assessed.
25
Laboratory practises Design circuits and programs in the laboratory sessions corresponding to the laboratory lessons 1 to 5.
It will be necessary to show to the professor the operation of each one of the circuits and programs.
It will be necessary to deliver the design source files.
The assessment will be based on the operation of the digital system and the correct application of the theoretical concepts, according to the published criteria.
<br>Through this methodology the outcomes CB5, CG8, CE11/TT11 and CE12/TT12 are assessed.
25
Integrated methodologies Project Based Learning.
Laboratory Project. Design of an embedded system.
It will be necessary to deliver the files source of the work realised.
It will be necessary to deliver the design source files.
The assessment will be based on the operation of the embedded system and the correct application of the theoretical concepts, according to the published criteria.
Through this methodology the outcomes CB5, CG1, CG8, CE11/TT11 and CE12/TT12 are assessed.
40
Presentations / exhibitions It will be necessary to do an oral presentation of 15 minutes as a maximum about the work, according to the index supplied by the teacher.

Through this methodology the outcomes CB5, CG1, CG8, CE11/TT11 and CE12/TT12 are assessed.
10
 
Other comments on the Evaluation
The total mark will be the sum of the marks obtained in the different tasks of the subject.

The global mark of the theoretical problems has to be equal or greater than 5 over 10 in order to pass the subject.
The mark of the Laboratory Project has to be equal or greater than 5 over 10 in order to pass the subject.

All the students, both those who follow the subject continuously and those who want to be assessed in the final exam at the end of the term or in the extraordinary exam in July, will have to do the tasks described in the previous section.
The students that do not attend classes regularly will also have to do the same tasks as the students who attend classes.

The final mark will be expressed in numerical form ranging from 0 to 10, according to the valid regulation (Royal decree 1125/2003 of 5 September; BOE 18 September).
Following the guidelines of the degree the students will be offered two assessment systems: continuous assessment and final assessment at the end of the term.

CONTINUOUS ASSESSMENT:
• The students are considered to have chosen the continuous assessment when they have done 2 laboratory practices and/or 2 reports of theoretical exercises.
• The students that have chosen continuous assessment, but do not pass the course, will have to do the final assessment in July.
• The students that pass the course by means of continuous assessment will not be allowed to repeat any task in the final assessment in order to improve the mark.
• The different tasks should be delivered in the date specified by the teacher, otherwise they will not be assessed for the continuous assessment.
• The students will develop the theoretical exercises, the laboratory practices and the laboratory projects in groups of two students during the continuous assessment.
The students who want to be assessed in the continuous assessment can only miss two sessions as a maximum.. If they miss more than 2 sessions, it will be compulsory to do an additional individual task or an examination.

FINAL ASSESSMENT:
• The students that opt for the final assessment will have to do all the theoretical and practical tasks and the project individually.
• The tasks for the final assessment have to be delivered before the official date of the examination set by the faculty.

In case the students pass the theoretical exercises (TE), the laboratory practices (LAB) and the laboratory project (LP), that is, the mark of each part >= 5, the final mark (FM) will be the weighted sum of the marks of each part of the subject:
NF = 0'25 * TE + 0'25 * LAB + 0'40 * LP + 0'10 * OP

In case the students do not pass any of the three main parts of the subject, that is, the mark of any task < 5, the final mark (FM) will be:
NF = Minimum [4'5; (NF = 0'25 * TE + 0'25 * LAB + 0'40 * LP + 0'10 * OP) ]

Where:
TE = Global mark of the theoretical exercises and problems.
LAB = Guided Laboratory Practices.
LP = Laboratory Project.
OP = Oral presentation.

ASSESSMENT CRITERIA.
1) Theoretical exercises and problems.
Each one of the theoretical exercises and problems proposed in the theoretical sessions will be marked from 0 to 10. Its influence in the total mark of the subject will be weighted in function of the number of exercises assigned.
The majority of the exercises will consist in the design of a peripheral for an embedded system embedded and the approach to the design of a complete embedded system with its peripherals.
The assessment criteria are the following:

1) Suitable distribution of tasks between “hardware” and “software".

2) Suitable organisation of the “hardware” and suitable structure of the program in C.

3) Correct design (CORR).
Optimisation of the description in VHDL and the programs in C.
Synchronous design.
Reusable design.

4) Functionality (FUNC). If the exercise asks for it, the behavioural simulation and synthesis of the VHDL, as well as the simulation of the C programs have to work perfectly.

5) Documentation (DOC).
i. Design source files.
ii. Enough comments in the VHDL files and C files to explain the sentences used.

It will be necessary to deliver the required source files.
The total mark will be the sum of the marks of each one of the exercise reports divided by the number of reports:

TE = (Exercise 1 + … + Exercise N) / N



2) Realisation of guided laboratory practices.

It will evaluate the correct operation of the circuits and programs developed in the laboratory sessions. Each laboratory lesson will be marked from 0 to 10. Its influence in the total mark of the subject will be weighted in function of the number of hours assigned to each lesson.
That is, the mark of the practices corresponding to the laboratory lessons 1 to 5 will be obtained through the following formula:

LAB = ( Lesson 1L + Lesson 2L + Lesson 3L + Lesson 4L + Lesson 5L ) / 5

The total mark of the guided laboratory practices (LAB) will correspond to 25% of the total mark of the subject.
It will be necessary to deliver the required source files.
The assessment criteria refer only to the functionality of the circuits and programs developed, that is, the circuits and programs have to work perfectly to obtain the maximum mark.


3) Laboratory Project.
This project consists in the design of an embedded system.

The assessment criteria are the following:

1) Suitable distribution of tasks between “hardware” and “software".

2) Suitable organisation of the hardware system and suitable structure of the program in C.

3) Correct design (CORR).
System entirely synthesisable.
Suitable hierarchy arrangement.
Design totally synchronous.
Technology independent design.
Reusable design.

4) Analysis of the design and the implementation in FPGAs (ANA).
Analysis of the FPGA logical resources used and their justification.
Analysis of the internal system delays.
Analysis of the chosen implementation options.
Optimal utilisation of the FPGA logical resources.
Achievement of an optimal processing speed.
‘Chipscope’ Verification.

5) Functionality (FUNC).
Software Simulation.
Software Debugging.
Behavioural and Timing Simulation of the different hardware circuits.
Simulation of the complete embedded system (hardware + software).
Debugging of the complete embedded system (hardware + software).
Board test of the complete embedded system (hardware + software).
All the sections have to work perfectly to obtain the maximum mark.

6) Documentation of the design and the implementation with FPGAs (DOC).
a. Document.
i. Clear structure and order.
ii. Clear and sufficient explanations for the understanding of the work developed.
iii. Include suitable figures.
iv. Include important data.

b. Source design files.
i. Sufficient comments in the VHDL files for its understanding.
ii. Sufficient comments in the C files for its understanding.

For the Laboratory Project (LP), it will be necessary to do an oral presentation.

4) Oral Presentation.

The work developed during the laboratory project will be presented.

The assessment criteria are the following:

1. Clear structure and presentation order.
2. Clear explanations.
3. Enough explanations to understand the project.
4. Suitable figures.
5. Relevant data.
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