Educational guide 2023_24 Escola de Enxeñaría de Telecomunicación

Máster Universitario en Ingeniería de Telecomunicación

Contents

Topic	Sub-topic
Unit 1: Introduction to mixed analog and digital electronic circuits.	Mixed circuits characteristics. Modeling, simulation and applications of mixed circuits. Introduction to hardware description languages for analog / digital mixed circuits.
Unit 2: Introduction to direct signal coupling techniques from analog to digital processors.	Introduction. Coupling technology in base band and by modulation. Measurement of time constants. PWM modulation. Sigma-Delta Modulation. Phase modulation. Frequency Modulation. Resources for coupling analog signals to digital processors.
Unit 3: Oversampling Techniques for digital processing of analog signals.	Oversampling techniques. Resolution gain. Reshaping of the quantization noise spectrum. First-order modulator. Modeling, simulation and test of sigma-delta modulators.
Unit 4: Sigma-delta modulators circuits.	Design of sigma-delta modulators with different topologies. Operating parameters. Low-pass and band-pass modulators.
Unit 5: Introduction to multistage A/D converters.	Pipelined A/D converters. Basic steps, timing and alignment. Test methods.
Unit 6: Digital filter circuits for signal sampling and reconstruction applications.	VHDL synthesis of digital filters. Decimation filters. Equalizer filters. Data format. Optimization.
Unit 7: Digital synthesis of signals to feed analog systems.	Methods of digital synthesis of analog signals. Direct synthesis. IIR filters. Modeling of digital synthesizers of analog signals with hardware description languages.
Laboratory sessions.	1.- Simulation of a Sigma-Delta ADC modulator. 2.- Assembly of a Sigma-Delta ADC modulator. 3.- Configuration of an FPGA to implement a Sigma-Delta DAC modulator. 4.- Configuration of an FPGA to implement a comb pass-2 filter. 5.- Configuration of an FPGA to implement a DDS circuit. 6.- Configuration of an FPGA to implement a synthesizer circuit based on IIR filter.