| Topic |
Sub-topic |
| Introdution to digital integrated circuits |
CMOS technology: NMOS and PMOS technologies, CMOS gates, CMOS fabrication.
HW design methodologies: custom, semicustom, cell-based, array-based, programmable logic devices (FPGAs).
SW design methodologies: abstraction levels, design methods, design flow, IPs. |
| Advanced VHDL |
VHDL description of complex digital systems: variables, arrays, records, generics, generate, funcion, procedure.
VHDL coding of Finite State Machines.
Advances synthesis: inference, primitives, IPs. |
| CMOS integrated circuits |
Design Metrics: voltages, noise, fan-in, fan-out, delay, power.
Power issues in FPGAs
Input/Output: standard levels, package.
Timing issues: set-up, hold, metastability, skew, jitter, clock distribution.
|
| Sequential design |
Synchronizers: asynchronous inputs, PLLs, DLLs
Clocking resources in FPGAs.
Sequential Design methods: Moore and Mealy Finite State Machines.
|
| Semiconductor memories |
Architecture of semiconductor memories: RAM, CAM, ROM, EEPROM, FLASH.
Memory Interfacing: RAM, DRAM, EEPROM, FLASH interfacing.
Memory in FPGAs: distributed, blocks, external memory, memory IPs.
|
| Arithmetic in FPGAs |
Numeric representations. Overflow. Techniques to mitigate overflow. Precision vs. hardware cost. Arithmetic operations. Low cost hardware implementations.
Design arithmetic considerations for HDL coding. |
| Frequency synthesis for communication applications |
Frequency synthesis using numerically controlled oscillators (NCOs). NCO architecture. Design parameters. Spurious Free Dynamic Range (SFDR) characterization. Design techniques.
NCO implementation using FPGAs. |
| Retiming and pipeline techniques |
Signal flow graphs (SFGs). Analysis of the critical path of digital systems. Analysis of the input to output latency. Retiming techniques to reduce propagation delay in digital systems: pipelining and time scaling.
Applying retiming techniques to the design of digital filters. Hardware cost.
Applying the concepts to the implementation of digital filters using FPGAs. |
| Series vs. parallel implementation issues |
Design techniques: fully serial, fully parallel, serial-parallel. Hardware cost and timing issues.
Applying the concepts to the implementation of digital filters using FPGAs. |
| Hardware-in-the-loop |
Description, simulation and test of FPGAs based circuits.
Applying the concepts to the design of data acquisition and signal processing circuits.
Using tools for hardware-in-the-loop. |
| Laboratory Practices |
Advanced tools for the design and test of complex digital circuits.
Design and implementation of ADC/DAC interfaces, sensor interfaces, digital signal processing modules, communications blocks and memory interfaces.
|
