| Topic |
Sub-topic |
| Chapter 1: Introduction (1h) |
Course introduction. Purposes and planning of the course. Basic concepts in the design of integrated circuits (ICs) and micro-electro-mechanical systems (MEMs). |
| Chapter 2: Fabrication steps for ICs and MEMs (2h) |
Introduction to ICs and MEMs fabrication. Planar technology. Micromachining and micromolding technologies. CMOS IC fabrication steps. Structure of MOS transistors. Fabrication example: CMOS inverter. Layout. MEMs fabrication steps: bulk micromachining, surface micromachining, and LIGA. |
| Chapter 3. ICs and MEMs fabrication processes (3h) |
Silicon wafers. Epitaxial layers. Dielectric layers. Oxidation. Deposition. Semiconductor layers. Dopant diffusion. Ion implantation. Photolithography. Etching. Metalization. |
| Chapter 4. Modeling of MOS transistors (3h). |
MOS transistors: analytical model. Higher-order effects. Fundamentals of Spice modeling and simulatin. Spice models of MOS transistors. |
| Chapter 5. Physical structure of basic elements (2h) |
Specification of the physical structure of a MOS transistor. Specification of the physical structure of a resistor. Specification of the physical structure of a capacitor. Types of physical specifications. Influence of physical design in the behavior of a device. Design rules. Design methodologies and tools. |
| Chapter 6. Resistor layout strategies (1h) |
Lateral diffusion. Effective geometric dimensions. Influence of the terminals. Long resistors. Unit resistors. Stacked resistors. Neighborhood effects. Dummies. Interdigited and common centroid structures. |
| Chapter 7. Capacitor layout strategies (1h) |
Oxide thickness gradient, lateral diffusion, and neighborhood effects. Area and perimeter unit capacitances. |
| Chapter 8. Transistor layout strategies (2h) |
Transistor with high aspect ratio. Stacked transistors. Interdigited structures. |
| Chapter 9. Physical design case studies (3h) |
Basic current mirror. Self-biased differential amplifier. |
| Lab assignment 1. Introduction to IC design tools (2h) |
Introduction to physical design tools. Basic layout elements and individual nMOS and pMOS transistors. Design Rule Check (DRC). Predesigned elements and transistors. |
| Lab assignment 2. CMOS inverter (4h) |
Schematic design of a CMOS inverter. Corrections for symmetrical response. Simulation with capacitive loads. Layout design and DRC. Layout Versus Schematic (LVS). Post-layout simulation (without and with capacitive load). Comparison with schematic simulation. |
| Lab assignment 3. MOS transsitor layout strategies (2h) |
Layout of pMOS and nMOS transistors. Snake, stacked, and interdigited structures. Dummy structures. |
| Lab assignment 4. Physical design of analog functional blocks: current mirror and differential pair (3h) |
Layouts of a basic curent mirror and a self-biased pMOS differential amplifier. |
| Lab assignment 5. Passive components layout strategies (2h) |
Layouts of resistors and capacitors. Linear, snake, stacked and interdigited structures. Dummy structures. |
