Guia docente 2013_14
Escuela de Ingeniería de Telecomunicación
Grao en Enxeñaría de Tecnoloxías de Telecomunicación
 Subjects
  Deseño e síntese de sistemas dixitais
   Assessment
  Description Qualification
Integrated methodologies Resolution of theoretical problems and exercises. The majority of them will be focused on the design of non-synthesisable models and synthesisable circuits in VHDL.

The problems will be based on the theoretical topcis.

It will be necessary to teach to the professor the operation of each one of the models and circuits.

The correct application of the theoretical concepts to the problems will be assessed, based on the published criteria.

It will be necessary to deliver the documentation requested by the professor for each one of the exercises.
50
Integrated methodologies Laboratory Project. Design of a medium-complexity synthesisable digital system in VHDL.

It will be necessary to deliver the design source files.

The assessment will be based on the operation of the digital system and the correct application of the theoretical concepts, according to the published criteria.
40
Presentations / exhibitions It will be necessary to do an oral presentation of 15 minutes as a maximum about the work, according to the index supplied by the teacher. 10
 
Other comments on the Evaluation

The total mark will be the sum of the marks obtained in the different tasks of the subject.



The global mark of the theoretical problems has to be equal or greater than 5 over 10 in order to pass the subject.


The mark of the Laboratory Project has to be equal or greater than 5 over 10 in order to pass the subject.



All the students, both those who follow the subject continuously and those who want to be assessed in the final exam at the end of the term or at the end of the year (second opportunity),  will have to do the tasks described in the previous section.


The students that do not attend classes regularly will also have to do the same tasks as the students who attend classes.



The final mark will be expressed in numerical form ranging from 0 to 10, according to the valid regulation (Royal decree 1125/2003 of 5 September; BOE 18 September).




Following the guidelines of the degree the students will be offered two assessment systems: continuous assessment and final assessment at the end of the term.



CONTINUOUS ASSESSMENT:


·        The students are considered to have chosen the continuous assessment when they have done 2  laboratory practices and/or 2 reports of theoretical exercises.


·        The students that have chosen continuous assessment, but do not pass the course, will have to do the final assessment at the end of the year.


·        The students that pass the course by means of continuous assessment will not be allowed to repeat any task in the final assessment in order to improve the mark.


·        The different tasks should be delivered in the date specified by the teacher, otherwise they will not be assessed for the continuous assessment.


·        The students will develop the theoretical exercises, the laboratory practices and the laboratory projects in groups of two students during the continuous assessment.


·        The students who want to be assessed in the continuous assessment can only miss two sessions as a maximum.. If they miss more than 2 sessions, it will be compulsory to do an additional individual task or an examination.




FINAL ASSESSMENT:


·        The students that opt for the final assessment will have to do all the theoretical and practical tasks and the project individually.


·        The tasks for the final assessment have to be delivered before the official date of the examination set by the faculty.



In case the students pass the theoretical exercises (TE) and the Laboratory Project (LP), that is, the mark of each part >= 5, the final mark (FM) will be the weighted sum of the marks of each part of the subject:


FM = 0'50 * TE + 0'40 * LP + 0'10 * OP



In case the students do not pass any of the two main parts of the subject, the theoretical exercises (TE) or the Laboratory Project (LP), that is, the mark of any task < 5, the final mark (FM) will be:


FM = Minimum [4'5; (FM = 0'50 * TE + 0'40 * LP + 0'10 * OP) ]



Where:


TE = Global mark of the theoretical exercises and problems.


LP = Laboratory Project.


OP = Oral presentation.



ASSESSMENT CRITERIA.



1) Theoretical exercises and problems.


Each one of the theoretical exercises and problems proposed in the theoretical sessions will be marked from 0 to 10. Its influence in the total mark of the subject will be weighted in function of the number of exercises assigned.


There will be eight reports of exercises.


The majority of the exercises will consist in the design of non-synthesisable models and synthesisable circuits in VHDL.


The assessment criteria are the following:



1.     Correct design (CORR).


a.     Behavioural model adequate to the project specifications.


b.     Synchronous design.


c.      Reusable design.



2.     Functionality (FUNC). For each one of the exercises, the behavioural circuit model has to work perfectly to obtain the maximum mark. If the circuit is synthesisable, the temporary simulation of the resultant circuit also has to work perfectly.


a.     Behavioural simulation.


b.     Synthesis.


c.      Timing simulation.



3.     Project documentation (DOC).


i.  Design source files.


ii.Enough comments in the VHDL files to explain the sentences used.



It will be necessary to deliver the required source files.


The total mark will be the sum of the marks of each one of the exercise reports divided by the number of reports:



TE = (Report 1 + … + Report 8) / 8



2) Laboratory Project.


This project consists in the design of a synthesisable digital system of medium complexity in VHDL.



The assessment criteria are the following:



1)     Correct design (CORR).


a.     System entirely synthesisable.


b.     Suitable hierarchy arrangement.


c.      Design totally synchronous.


d.     Technology independent design.


e.     Reusable design.



2)     Analysis of the design and the implementation in FPGAs (ANA).


a.     Analysis of the FPGA logical resources used and their justification.


b.     Analysis of the internal system delays.


c.      Analysis of the chosen implementation options.


d.     Optimal utilisation of the FPGA logical resources.


e.     Achievement of an optimal processing speed.


f.       ‘Chipscope’ Verification.



3)     Functionality (FUNC). For each circuit, the behavioral simulation, the timing simulation and the board test should work perfectly to obtain the maximum mark.


a.     Individual circuits.


b.     Complete system.



4) Documentation (DOC).


i.       Design source files.


1.     Enough comments in the VHDL files to explain the sentences used.




For the Laboratory Project (LP), it will be necessary to do an oral presentation.



3) Oral Presentation.



1.     Clear structure and presentation order.


2.     Clear explanations.


3.     Enough explanations to understand the project.


4.     Suitable figures.


5.     Relevant data.



 

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