| Integrated methodologies |
Problem based learning (PBL): Problem solving. Design of non- synthesisable models and synthesisable circuits in VHDL. To solve them, the student has to previously develop certain outcomes.
Through this methodology the outcomes CG9, CG13 and CE62/OP5 are developed. |
| Integrated methodologies |
Project based learning. The students must design a digital system in VHDL to solve a problem. In order to that, the students must plan, design and implement the necessary steps.
The project development will be implemented in laboratory hours (type B).
Besides, in type C hours there will be discussions and one-to-one interaction with the teacher.
Activities to develop in the groups C:
Analysis and debate about the project approach and different alternatives.
Analysis and follow-up of the proposed solution.
Design implementation. Analysis and debate of results.
Oral presentations of the project results.
Through this methodology the outcomes CG1, CG9, CG13 and CE62/OP5 are developed. |
| Introductory activities |
Introduction to the subject key topics both theoretical and practical.
Through this methodology the outcomes CG13 and CE62/OP5 are developed. |
