Guia docente 2013_14
Escuela de Ingeniería de Telecomunicación
Grao en Enxeñaría de Tecnoloxías de Telecomunicación
 Subjects
  Deseño e síntese de sistemas dixitais
   Learning aims
Expected results from this subject Typology Training and Learning Results
To be able to distinguish the differences between the use of Hardware Description Languages for simulation and for synthesis.
know
 A71
To deepen the understanding of synchronous digital design techniques using VHDL for synthesis.
know
 A71
To acquire skills at designing complex synchronous digital systems using VHDL.
know
 A1
A9
To use the hardware and software tools available for the design of digital systems by means of VHDL and for their implementation on programmable digital circuits.
Know How
 A1
A9
 B4
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