| Topic |
Sub-topic |
| Chapter 1: Introduction (1h) |
Course introduction. Purposes and planning of the course. Basic concepts in the design of integrated circuits (ICs) and micro-electro-mechanical systems (MEMs). |
| Chapter 2: Fabrication steps for ICs and MEMs (2h) |
Introduction to ICs and MEMs fabrication. Planar technology. Micromachining and micromolding technologies. CMOS IC fabrication steps. Structure of MOS transistors. Fabrication example: CMOS inverter. Layout. MEMs fabrication steps: bulk micromachining, surface micromachining, and LIGA. |
| Chapter 3. ICs and MEMs fabrication processes (3h) |
Silicon wafers. Epitaxial layers. Dielectric layers. Oxidation. Deposition. Semiconductor layers. Dopant diffusion. Ion implantation. Photolithography. Etching. Metalization. |
| Chapter 4. CMOS process parameters (3h). |
MOS transistors: analytical model. Higher-order effects. Spice model. Technology file. Parameters of a sample CMOS process. |
| Chapter 5. Physical structure of basic elements (2h) |
Specification of the physical structure of a MOS transistor. Specification of the physical structure of a resistor. Specification of the physical structure of a capacitor. Types of physical specifications. Influence of physical design in the behavior of a device. Design rules. Design methodologies and tools. |
| Chapter 6. Resistor layout strategies (1h) |
Lateral diffusion. Effective geometric dimensions. Influence of the terminals. Long resistors. Unit resistors. Stacked resistors. Neighborhood effects. Dummies. Interdigited and common centroid structures. |
| Chapter 7. Capacitor layout strategies (1h) |
Oxide thickness gradient, lateral diffusion, and neighborhood effects. Area and perimeter unit capacitances. |
| Chapter 8. Transistor layout strategies (2h) |
Transistor with high aspect ratio. Stacked transistors. Interdigited structures. |
| Chapter 9. Physical design case studies (3h) |
Basic current mirror. Self-biased differential amplifier. |
| Lab assignment 1. Introduction to IC design tools (3h) |
Basic layout elements. Design Rule Check (DRC). Extraction. Basic layout elements from libraries. |
| Lab assignment 2. MOS transistors (3h) |
Layout of pMOS and nMOS transistors. Transistors from libraries. Snake, stacked, and interdigited structures. Dummy definition layers. |
| Lab assignment 3. Passive components (2h) |
Layouts of resistors and capacitors. Resistors and capacitors from libraries. Linear, snake, stacked and interdigited structures. |
| Lab assignment 4. CMOS inverter (1h) |
Schematic and layout of a CMOS inverter. Layout Versus Schematic (LVS). Layout extraction. Post-layout simulation. |
| Lab assignment 5. Current mirror (2h) |
Schematic and layout of a basic curent mirror with resistive load and ideal input current source. LVS. Layout extraction. |
| Lab assignment 6. Differential amplifier (2h) |
Schematic and layout of a self-biased pMOS differential amplifier. LVS. Layout extraction. |
