Guia docente 2016_17 Escola de Enxeñaría de Telecomunicación

Learning outcomes

Expected results from this subject	Training and Learning Results
To be able to distinguish the differences between the use of Hardware Description Languages for simulation and for synthesis.		B13	C62
To deepen the understanding of synchronous digital design techniques using VHDL for synthesis.		B13	C62
To acquire skills at designing complex synchronous digital systems using VHDL.		B1 B9 B13	C62	D4